The present invention relates generally the fabrication of semiconductor devices, and more specifically to forming borderless contacts to the semiconductor devices.
Field-effect transistors (FETs) are commonly employed in electronic circuit applications. FETs may include a semiconductor substrate containing a source region and a drain region spaced apart by a channel region. A gate electrode may be formed above the channel region. In part to protect the gate electrode, insulating spacers and a hard cap may be formed on the side and top, respectively, of the gate electrode. The gate electrode may then be surrounded by a dielectric layer formed above the FET. By applying voltage to the gate electrode, the conductivity of the channel region may increase and allow current to flow from the source region to the drain region.
To allow current to flow between the source and drain region, electrical contacts may be formed on the source region and the drain region. The contacts may be formed by etching contact holes in the dielectric layer. As transistor structures continue to become smaller in size, it becomes increasingly difficult to lithographically define the borders of the contact holes. As a result, techniques may be developed to use the insulating spacers and hard cap of the gate electrode to form borderless, self-aligned contacts. Borderless contacts may be formed so that there is no remaining material of the dielectric layer between the borderless contact and the spacers and hard cap of the FET. By using the spacers and hard cap to define the contact, it may be possible to maximize the interface between the contact and the source/drain region while also utilizing a less precise lithographic process.
However, the etching processes used to define the contact may result in damage to the spacers and hard cap. This damage may further result in damage to the gate electrode or shorting between the gate electrode and electrical contact. Therefore, a process for forming self-aligned contacts that maintains the integrity of the gate spacers and gate hard cap may be desirable.